The present invention relates to a semiconductor nonvolatile memory of the floating gate type operable to electrically effect writing and erasing of data.
FIG. 4 is a sectional view of a memory cell of the conventional nonvolatile memory operable to electrically effect writing and erasing of data (hereinafter, referred to as an "EEPROM"). FIG. 5 is a sectional view of a peripheral circuit of the conventional nonvolatile memory operable to electrically effect writing and erasing of data.
Firstly, the memory cell of FIG. 4 is briefly explained. A source region 102 of N.sup.+ type, a drain region 103 of N.sup.+ type and a tunnel-drain region 123 of N.sup.+ type are concurrently formed in a surface portion of P type semiconductor substrate 101. Then, a gate electrode 125 of the memory cell is formed on the substrate through a gate oxide film 104 of the memory cell, and at the same time a floating gate electrode 105 is formed on the substrate through a tunnel oxide film 106. Further, a control gate electrode 107 is formed on the floating gate electrode 105 through second gate oxide film 109 so as to control the potential level of the floating gate electrode 105. The injecting and extracting operations of electric charge to and from the floating gate electrode 105 are carried out through the tunnel oxide film 106 formed on the tunnel-drain region 123.
Next, the peripheral circuit of FIG. 5 is briefly explained. An n-well region 110 and a field oxide film 111 are formed in the P type silicon substrate 101. An N.sup.+ type source region 112 and N.sup.+ type drain region 113 are formed in a P type region of the P type silicon substrate 101, and a gate electrode 115 is formed thereon through a gate oxide film 114. A P.sup.+ type source region 116 and P.sup.+ type drain region 117 are formed in the n-well region 110, and another gate electrode 115 is formed thereon through the gate oxide film 114. The second gate oxide film 109 of the memory cell is formed concurrently with the gate oxide film 114 of the peripheral circuit.
As shown in FIG. 4, since the second gate oxide film 109 of the memory cell is formed on the floating gate electrode 105 composed of polysilicon layer, the second gate oxide film 109 must undergo a heating process above a temperature of 1050.degree. C. in order to improve its film quality. However, when carrying out the heating process over 1050.degree. C. after forming the tunnel oxide film 106 under the floating gate electrode 105, the film quality of the oxide film 106 is degradated which causes the drawback that the writing feature of the EEPROM is impaired. The possible repetition cycles of the writing operation in the conventional EEPROM is illustrated in FIG. 3 as dushed lines, in which the abscissa indicates the repetition cycle number of alternate writing and erasing operations and the ordinate indicates threshold voltage V.sub.th.